EH1400SJETTTS-25.00062M
REGULATORY COMPLIANCE
2011/65 +
2015/863
(Data Sheet downloaded on Aug 27, 2020)
191 SVHC
ITEM DESCRIPTION
Quartz Crystal Clock Oscillators XO (SPXO) HCMOS/TTL (CMOS) 5.0Vdc J-Lead 9.8mm x 14.0mm Plastic Surface Mount (SMD)
25.00062MHz ±100ppm -40°C to +85°C
ELECTRICAL SPECIFICATIONS
Nominal Frequency
Frequency Tolerance/Stability
Aging at 25°C
Operating Temperature Range
Supply Voltage
Input Current
Output Voltage Logic High (Voh)
Output Voltage Logic Low (Vol)
Rise/Fall Time
Duty Cycle
Load Drive Capability
Output Logic Type
Pin 1 Connection
Tri-State Input Voltage (Vih and Vil)
Absolute Clock Jitter
One Sigma Clock Period Jitter
Start Up Time
Storage Temperature Range
25.00062MHz
±100ppm Maximum (Inclusive of all conditions: Calibration Tolerance at 25°C, Frequency Stability over the Operating
Temperature Range, Supply Voltage Change, Output Load Change, First Year Aging at 25°C, Shock, and Vibration)
±5ppm/year Maximum
-40°C to +85°C
5.0Vdc ±10%
50mA Maximum (No Load)
2.4Vdc Minimum with TTL Load, Vdd-0.4Vdc Minimum with HCMOS Load, IOH = -16mA
0.4Vdc Maximum with TTL Load, 0.5Vdc Maximum with HCMOS Load, IOL = +16mA
6nSec Maximum (Measured at 0.8Vdc to 2.0Vdc with TTL Load; Measured at 20% to 80% of waveform with HCMOS
Load)
50 ±5(%) (Measured at 50% of waveform with TTL Load or with HCMOS Load)
10TTL Load or 50pF HCMOS Load Maximum
CMOS
Tri-State (Disabled Output: High Impedance)
+2.2Vdc Minimum to enable output, +0.8Vdc Maximum to disable output (High Impedance), No Connect to enable
output.
±250pSec Maximum, ±100pSec Typical
±50pSec Maximum, ±30pSec Typical
10mSec Maximum
-55°C to +125°C
ENVIRONMENTAL & MECHANICAL SPECIFICATIONS
ESD Susceptibility
Fine Leak Test
Flammability
Gross Leak Test
Mechanical Shock
Moisture Resistance
Resistance to Soldering Heat
Resistance to Solvents
Solderability
Temperature Cycling
Vibration
MIL-STD-883, Method 3015, Class 1, HBM: 1500V
MIL-STD-883, Method 1014, Condition A (Internal Crystal Only)
UL94-V0
MIL-STD-883, Method 1014, Condition C (Internal Crystal Only)
MIL-STD-202, Method 213, Condition C
MIL-STD-883, Method 1004
MIL-STD-202, Method 210, Condition K
MIL-STD-202, Method 215
MIL-STD-883, Method 2003
MIL-STD-883, Method 1010, Condtion B
MIL-STD-883, Method 2007, Condition A
www.ecliptek.com | Specification Subject to Change Without Notice | Revision F 08/14/2012 | Page 1 of 6
Ecliptek, LLC
5458 Louie Lane, Reno, NV 89511
1-800-ECLIPTEK or 714.433.1200
EH1400SJETTTS-25.00062M
MECHANICAL DIMENSIONS (all dimensions in millimeters)
PIN
5.080
±0.203
1
0.25 MIN
2
4
7.620
±0.203
9.8
MAX
3
3
4
MARKING
ORIENTATION
1
2
14.0
MAX
CONNECTION
Tri-State (High
Impedance)
Ground
Output
Supply Voltage
LINE MARKING
1
2
3
ECLIPTEK
25.000M
XXXXX
XXXXX=Ecliptek
Manufacturing Identifier
0.510 ±0.203
4.7
MAX
Suggested Solder Pad Layout
All Dimensions in Millimeters
1.27 (X4)
3.0 (X4)
5.8
Solder Land
(X4)
3.81
All Tolerances are ±0.1
www.ecliptek.com | Specification Subject to Change Without Notice | Revision F 08/14/2012 | Page 2 of 6
Ecliptek, LLC
5458 Louie Lane, Reno, NV 89511
1-800-ECLIPTEK or 714.433.1200
EH1400SJETTTS-25.00062M
OUTPUT WAVEFORM & TIMING DIAGRAM
TRI-STATE INPUT
V
IH
V
IL
CLOCK OUTPUT
V
OH
80% or 2.0V
DC
50% or 1.4V
DC
20% or 0.8V
DC
V
OL
OUTPUT DISABLE
(HIGH IMPEDANCE
STATE)
t
PLZ
Fall
Time
Rise
Time
T
W
T
Duty Cycle (%) = T
W
/T x 100
t
PZL
www.ecliptek.com | Specification Subject to Change Without Notice | Revision F 08/14/2012 | Page 3 of 6
Ecliptek, LLC
5458 Louie Lane, Reno, NV 89511
1-800-ECLIPTEK or 714.433.1200
EH1400SJETTTS-25.00062M
Test Circuit for CMOS Output
Oscilloscope
Frequency
Counter
+
+
Power
Supply
_
+
Voltage
Meter
_
Current
Meter
_
Supply
Voltage
(V
DD
)
Probe
(Note 2)
Output
0.01µF
(Note 1)
0.1µF
(Note 1)
Ground
C
L
(Note 3)
Tri-State
Note 1: An external 0.01µF ceramic bypass capacitor in parallel with a 0.1µF high frequency ceramic bypass
capacitor close (less than 2mm) to the package ground and supply voltage pin is required.
Note 2: A low capacitance (<12pF), 10X attenuation factor, high impedance (>10Mohms), and high bandwidth
(>300MHz) passive probe is recommended.
Note 3: Capacitance value C
L
includes sum of all probe and fixture capacitance.
www.ecliptek.com | Specification Subject to Change Without Notice | Revision F 08/14/2012 | Page 4 of 6
Ecliptek, LLC
5458 Louie Lane, Reno, NV 89511
1-800-ECLIPTEK or 714.433.1200
EH1400SJETTTS-25.00062M
Test Circuit for TTL Output
Output Load
Drive Capability
10TTL
5TTL
R
L
Value
(Ohms)
390
780
C
L
Value
(pF)
15
15
Oscilloscope
Frequency
Counter
Table 1: R
L
Resistance Value and C
L
Capacitance
Value Vs. Output Load Drive Capability
Supply
Voltage
(V
DD
)
Probe
(Note 2)
Output
R
L
(Note 4)
+
+
Power
Supply
_
+
Voltage
Meter
_
Current
Meter
_
+
0.01µF
(Note 1)
0.1µF
(Note 1)
C
L
(Note 3)
Power
Supply
_
Ground
Tri-State
Note 1: An external 0.01µF ceramic bypass capacitor in parallel with a 0.1µF high frequency ceramic bypass
capacitor close (less than 2mm) to the package ground and supply voltage pin is required.
Note 2: A low capacitance (<12pF), 10X attenuation factor, high impedance (>10Mohms), and high bandwidth
(>300MHz) passive probe is recommended.
Note 3: Capacitance value C
L
includes sum of all probe and fixture capacitance.
Note 4: Resistance value R
L
is shown in Table 1. See applicable specification sheet for 'Load Drive Capability'.
Note 5: All diodes are MMBD7000, MMBD914, or equivalent.
www.ecliptek.com | Specification Subject to Change Without Notice | Revision F 08/14/2012 | Page 5 of 6
Ecliptek, LLC
5458 Louie Lane, Reno, NV 89511
1-800-ECLIPTEK or 714.433.1200
